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rev. 1.1 11/11 copyright ? 2011 by silicon laboratories si473x-d60 si4730/31/34/35-d60 b roadcast am/fm/sw/lw r adio r eceiver features applications description the si473x-d60 digital cmos am/fm radio receiver ic integrates the complete tuner function from antenna input to digi tal audio output and includes a stereo audio auxin adc input for converting analog audio into standard i2s digital audio, enabling a cost efficient digital audio platform for consumer electronic applications with high tdma noise immuni ty, superior radio performance, and high fidelity audio power amplification. when enabling the analog inputs in stereo auxin adc-mode, the si473x-d60 supports i2s digital audio output only (no analog output). functional block diagram ? worldwide fm band support (64?108 mhz) ? worldwide am band support (520?1710 khz) ? sw band support (si4734/35) (2.3?26.1 mhz) ? lw band support (si4734/35) (153?279 khz) ? excellent real-world performance ? integrated vco ? advanced am/fm seek tuning ? automatic frequency control (afc) ? automatic gain control (agc) ? digital fm stereo decoder ? programmable de-emphasis ? advanced audio processing ? multiplexed stereo audio auxin adc with 85 db dynamic range ? seven selectable am channel filters ? am/fm/sw/lw digital tuning ? en55020 compliant ? no manual alignment necessary ? programmable reference clock ? adjustable soft mute control ? rds/rbds processor (si4731/35) ? digital audio out ? 2-wire and 3-wire control interface ? integrated ldo regulator ? wide range of ferrite loop sticks and air loop antennas supported ? qfn and ssop packages ?? rohs compliant ? table and portable radios ? mini/micro systems ? cd/dvd and blu-ray players ? stereo boom boxes ? modules for consumer electronics ? clock radios ? mini hifi and docking stations ? entertainment systems adc si473x-d60 dsp dac lout rout afc gpo/dclk ldo va 2.7~5.5 v (qfn) 2.0~5.5 v (ssop) rds (si4731/ 35) ami vd 1.62 - 3.6 v sen control interface sclk lna agc lna agc gnd adc mux mux dac low-if sdio rst digital audio dfs dout lin rin rclk am / lw ant rfgnd fmi fm / sw ant + this product, its features, and/or its architecture is covered by one or more of the following patents, as well as other patents, pending and issued, both foreign and domestic: 7,127,217; 7,272,373; 7,27 2,375; 7,321,324; 7,355,476; 7,42 6,376; 7,471,940; 7,339,503; 7,339,504. ordering information: see page 33. pin assignments si473x-d60(ssop) si473x-d60 (qfn) gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 gpo2/[int] vd dout/[lin] lout/[dfs] rout/[dout] gnd rst nc ami rclk sdio va fmi rfgnd gpo3/[dclk] nc gpo1 dfs/[rin] sclk sen lout/[dfs] rout/[dout] dbyp vd gpo2/[int] gpo3/[dclk] dout/[lin] dfs/[rin] 1 2 3 4 5 6 7 8 9 10 11 12 gpo1 va sdio nc nc rclk sen fmi rfgnd sclk gnd nc nc rst gnd ami 24 23 22 21 20 19 18 17 16 15 14 13
si4730/31/34/35-d60 2 rev. 1.1
si4730/31/34/35-d60 rev. 1.1 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1. qfn typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2. ssop typical applic ation schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1. qfn/ssop bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3. fm receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4. am receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5. sw receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 4.6. lw receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7. stereo audio auxin adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8. digital audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.9. stereo audio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.10. received signal qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.11. volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.12. stereo dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 4.13. soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.14. fm hi-cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.15. de-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.16. rds/rbds processor (si4731/35 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4.17. tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.18. seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.19. reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.20. control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 4.21. gpo outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.22. firmware upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.23. reset, powerup, and powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.24. 2 v operation (ssop only ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.25. programming wi th commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1. si473x-d60-gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.2. si473x-d60-gu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1. si473x-d60 qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2. si473x-d60 ssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8. pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
si4730/31/34/35-d60 4 rev. 1.1 8.1. si473x-d60 qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.2. si473x-d60 ssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9. top markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 9.1. si473x-d60 top marking (qfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2. top marking explanation (qfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.3. si473x-d60 top marking (ssop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.4. top marking explanation ( ssop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10. additional reference resour ces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
si4730/31/34/35-d60 rev. 1.1 5 1. electrical specifications table 1. recommended operating conditions 1 parameter symbol test condition min typ max unit analog supply voltage v a 2.7 2 ?5.5 v digital and i/o supply voltage v d 1.62 ? 3.6 v power supply powe rup rise time v ddrise 10 ? ? s interface power supply powerup rise time v iorise 10 ? ? s ambient temperature t a ?20 25 85 ? c notes: 1. all minimum and maximum specifications apply across the re commended operating conditions . typical values apply at v a = 3.3 v and 25 ? c unless otherwise stated. 2. ssop devices operate down to 2 v at 25 c. see sect ion ?4.24. 2 v operation (ssop only)? for details.
si4730/31/34/35-d60 6 rev. 1.1 table 2. dc characteristics (v a = 2.7 to 5.5 v, v d = 1.62 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit fm mode v aqfn supply current i fmva digital output mode 1 ?8.29.5 ma v dqfn supply current i fmvd ? 10.5 13.5 v assop supply current i fmva ? 18.5 21.5 v dssop supply current i fmvd ? 0.15 0.6 v aqfn supply current i fmva analog output mode 2 ?9.110.3 v dqfn supply current i fmvd ?9.912.8 v assop supply current i fmva ? 19.1 21.3 v dssop supply current i fmvd 0.1 0.6 am mode v aqfn supply current i amva digital output mode ?6.57.5 ma v dqfn supply current i amvd ? 8.5 11.0 v assop supply current i amva ? 14.5 16.5 v dssop supply current i amvd ? 0.15 0.50 v aqfn supply current i amva analog output mode ?7.58.5 v dqfn supply current i amvd ?810.2 v assop supply current i amva ? 15.3 17.2 v dssop supply current i amvd ?0.10.4 auxin mode v aqfn supply current i auxva ?5.76.3 ma v dqfn supply current i auxvd ?6.58.0 v assop supply current i auxva ?0.30.4 v dssop supply current i auxvd ?11.813.0 powerdown v aqfn powerdown current i apd ?415 a v assop powerdown current ? 9.5 15 v dqfn powerdown current i dpd sclk, rclk inactive ? 3 10 a v dssop powerdown current sclk, rclk inactive ? 3 10 high level input voltage 3 v ih 0.7 x v d ?v d +0.3 v low level input voltage 3 v il ?0.3 ? 0.3 x v d v high level input current 3 i ih v in =v d =3.6v ?10 ? 10 a notes: 1. guaranteed by characterization. 2. backwards compatible mode to rev b and rev c. additional f eatures on this device may increase typical supply current. 3. for input pins sclk, sen, sdio, rst, rcl k, dclk, dfs, gpo1, gpo2, and gpo3. 4. for output pins sdio, dout, gpo1, gpo2, and gpo3.
si4730/31/34/35-d60 rev. 1.1 7 low level input current 3 i il v in =0v, v d =3.6v ?10 ? 10 a high level output voltage 4 v oh i out = 500 a 0.8 x v d ??v low level output voltage 4 v ol i out = ?500 a ? ? 0.2 x v d v table 2. dc characteristics (continued) (v a = 2.7 to 5.5 v, v d = 1.62 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit notes: 1. guaranteed by characterization. 2. backwards compatible mode to rev b and rev c. additional f eatures on this device may increase typical supply current. 3. for input pins sclk, sen, sdio, rst, rcl k, dclk, dfs, gpo1, gpo2, and gpo3. 4. for output pins sdio, dout, gpo1, gpo2, and gpo3.
si4730/31/34/35-d60 8 rev. 1.1 figure 1. reset timing parameters for busmode select table 3. reset timing characteristics 1,2,3 (v a = 2.7 to 5.5 v, v d = 1.62 to 3.6 v, t a = ?20 to 85 c) parameter symbol min typ max unit rst pulse width and gpo1, gpo2/int setup to r st ? ? t srst 100 ? ? s gpo1, gpo2/int hold from r st ? t hrst 30 ? ? ns important notes: 1. when selecting 2-wire mode, the user must ensure that a 2- wire start condition (falling edge of sdio while sclk is high) does not occur within 300 ns before the rising edge of rst . 2. when selecting 2-wire mode, the user must ensure t hat sclk is high during the rising edge of rst , and stays high until after the first start condition. 3. when selecting 3-wire mode, the user must ensure that a ri sing edge of sclk does not occur within 300 ns before the rising edge of rst . 4. if gpo1 and gpo2 are actively driven by the user, then minimum t srst is only 30 ns. if gpo1 or gpo2 is hi-z, then minimum t srst is 100 s, to provide time for on-chip 1 m ? devices (active while rst is low) to pull gpo1 high and gpo2 low. 70% 30% gpo1 70% 30% gpo2/ int 70% 30% t srst rst t hrst
si4730/31/34/35-d60 rev. 1.1 9 table 4. 2-wire control interface characteristics 1,2,3 (v a = 2.7 to 5.5 v, v d = 1.62 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk frequency f scl 0?400khz sclk low time t low 1.3 ? ? s sclk high time t high 0.6 ? ? s sclk input to sdio ? setup (start) t su:sta 0.6 ? ? s sclk input to sdio ? hold (start) t hd:sta 0.6 ? ? s sdio input to sclk ? setup t su:dat 100 ? ? ns sdio input to sclk ? hold 4,5 t hd:dat 0?900ns sclk input to sdio ? setup (stop) t su:sto 0.6 ? ? s stop to start time t buf 1.3 ? ? s sdio output fall time t f:out ?250ns sdio input, sclk rise/fall time t f:in t r:in ?300ns sclk, sdio capacitive loading c b ??50pf input filter pu lse suppression t sp ? ? 50 ns notes: 1. when v d = 0 v, sclk and sdio are low impedance. 2. when selecting 2-wire mode, the user must ensure that a 2- wire start condition (falling edge of sdio while sclk is high) does not occur within 300 ns before the rising edge of rst . 3. when selecting 2-wire mode, the user must ensure th at sclk is high during the rising edge of rst , and stays high until after the first start condition. 4. the si473x-d60 delays sdio by a minimum of 300 ns from the v ih threshold of sclk to comply with the minimum t hd:dat specification. 5. the maximum t hd:dat has only to be met when f scl = 400 khz. at frequencies below 400 khz, t hd:dat may be violated as long as all other timing parameters are met. 20 0.1 c b 1pf ---------- - + 20 0.1 c b 1pf ---------- - +
si4730/31/34/35-d60 10 rev. 1.1 figure 2. 2-wire control interface read and write timing parameters figure 3. 2-wire control interface read and write timing diagram sclk 70% 30% sdio 70% 30% start start stop t f:in t r:in t low t high t hd:sta t su:sta t su:sto t sp t buf t su:dat t r:in t hd:dat t f:in, t f:out sclk sdio start stop address + r/w ack data ack data ack a6-a0, r/w d7-d0 d7-d0
si4730/31/34/35-d60 rev. 1.1 11 figure 4. 3-wire control interface write timing parameters figure 5. 3-wire control interface read timing parameters table 5. 3-wire control interface characteristics (v a = 2.7 to 5.5 v, v d = 1.62 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk frequency f clk 0?2.5mhz sclk high time t high 25 ? ? ns sclk low time t low 25 ? ? ns sdio input, sen to sclk ?? setup t s 20 ? ? ns sdio input to sclk ?? hold t hsdio 10 ? ? ns sen input to sclk ? ? hold t hsen 10 ? ? ns sclk ?? to sdio output valid t cdv read 2 ? 25 ns sclk ?? to sdio output high z t cdz read 2 ? 25 ns sclk, sen , sdio, rise/fall time t r , t f ? ? 10 ns note: when selecting 3-wire mode, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . sclk 70% 30% sen 70% 30% sdio a7 a0 70% 30% t s t s t hsdio t hsen a6-a5, r/w, a4-a1 address in data in d15 d14-d1 d0 t high t low t r t f ? cycle bus turnaround sclk 70% 30% sen 70% 30% sdio 70% 30% t hsdio t cdv t cdz address in data out a7 a0 a6-a5, r/w, a4-a1 d15 d14-d1 d0 t s t s t hsen
si4730/31/34/35-d60 12 rev. 1.1 figure 6. digital audio interface timing parameters, i 2 s mode table 6. digital audio interface characteristics (v a = 2.7 to 5.5 v, v d = 1.62 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit dclk cycle time t dct 26 ? 1000 ns dclk pulse width high t dch 10 ? ? ns dclk pulse width low t dcl 10 ? ? ns dfs set-up time to dclk rising edge t su:dfs 5?? ns dfs hold time from dclk rising edge t hd:dfs 5?? ns dout propagation delay from dclk falling edge t pd:dout 0?50ns dclk dfs t dct t pd:out t su:dfs t hd:dfs dout t dch t dcl
si4730/31/34/35-d60 rev. 1.1 13 table 7. fm receiver characteristics 1,2 (v a = 2.7 to 5.5 v, v d = 1.62 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit input frequency f rf 76 ? 108 mhz sensitivity 3,4,5,6 (s+n)/n = 26 db ? 2.2 3.5 v emf rds sensitivity 6,7 ? f = 2 khz, rds bler < 5% ?10?v emf lna input resistance 7,8 345 k ? lna input capacitance 7,8 456 pf input ip3 7,9 100 105 ? dbv emf am suppression 3,4,7,8 m = 0.3 40 50 ? db adjacent channel selectivity 200 khz 35 50 ? db alternate channel selectivity 400 khz 60 70 ? db spurious response rejection 7 in-band 35 ? ? db audio output voltage 3,4,8 72 80 90 mv rms audio output l/r imbalance 3,8,10 ?? 1 db audio frequency response low 7 ?3 db ? ? 30 hz audio frequency response high 7 ?3 db 15 ? ? khz audio stereo separation 8,10 35 42 ? db audio mono s/n 3,4,5,8 55 63 ? db audio stereo s/n 4,5,7,8 ?58? db audio thd 3,8,10 ?0.10.5 % de-emphasis time constant 7 fm_deemphasis = 2 70 75 80 s fm_deemphasis = 1 45 50 54 s blocking sensitivity 3,4,5,6,7,11, 12 ? f = 400 khz ? 34 ? dbv ? f = 4 mhz ? 30 ? dbv notes: 1. additional testing information is available in ?an388: si470x/1x/2x/3x/4x evaluatio n board test procedure.? volume = maximum for all tests. tested at rf = 98.1 mhz. 2. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout, and design guidelines.? silico n laboratories will evaluate schematics and layouts for qualified customers. 3. f mod =1khz, 75 s de-emphasis, mono = enabled, and l = r unless noted otherwise. 4. ? f = 22.5 khz. 5. b af = 300 hz to 15 khz, a-weighted. 6. analog audio output mode. 7. guaranteed by characterization. 8. v emf =1 mv. 9. |f 2 ? f 1 | > 2 mhz, f 0 =2xf 1 ? f 2 . agc is disabled. 10. ? f = 75 khz. 11. sensitivity measured at (s+n)/n = 26 db. 12. blocker amplitude = 100 dbuv. 13. at temperature (25 c). 14. at lout and rout pins.
si4730/31/34/35-d60 14 rev. 1.1 intermod sensitivity 3,4,5,6,7,11,12 ? f = 400 khz, 800 khz ? 40 ? dbv ? f = 4 mhz, 8 mhz ? 35 ? dbv audio output load resistance 7,11,14 r l single-ended 10 ? ? k ? audio output load capacitance 7,11,14 c l single-ended ? ? 50 pf seek/tune time 7 rclk tolerance =100ppm ? ? 60 ms/channel powerup time 7 from powerdown ? ? 110 ms rssi offset 12,13 input levels of 8 and 60 dbv at rf input ?3 ? 3 db table 7. fm receiver characteristics 1,2 (continued) (v a = 2.7 to 5.5 v, v d = 1.62 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit notes: 1. additional testing information is available in ?an388: si470x/1x/2x/3x/4x evaluatio n board test procedure.? volume = maximum for all tests. tested at rf = 98.1 mhz. 2. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout, and design guidelines.? silico n laboratories will evaluate schematics and layouts for qualified customers. 3. f mod =1khz, 75 s de-emphasis, mono = enabled, and l = r unless noted otherwise. 4. ? f = 22.5 khz. 5. b af = 300 hz to 15 khz, a-weighted. 6. analog audio output mode. 7. guaranteed by characterization. 8. v emf =1 mv. 9. |f 2 ? f 1 | > 2 mhz, f 0 =2xf 1 ? f 2 . agc is disabled. 10. ? f = 75 khz. 11. sensitivity measured at (s+n)/n = 26 db. 12. blocker amplitude = 100 dbuv. 13. at temperature (25 c). 14. at lout and rout pins.
si4730/31/34/35-d60 rev. 1.1 15 table 8. 64?75.9 mhz input frequency fm receiver characteristics 1,2,3 (v a = 2.7 to 5.5 v, v d = 1.62 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit input frequency f rf 64 ? 75.9 mhz sensitivity 4,5,6 , 8 (s+n)/n = 26 db ? 3.5 ? v emf lna input resistance 3,7 345 k ? lna input capacitance 3,7 456 pf input ip3 9 ? 105 ? dbv emf am suppression 3,4,5,7 m = 0.3 ? 50 ? db adjacent channel selectivity 200 khz ? 50 ? db alternate channel selectivity 400 khz ? 70 ? db audio output voltage 4,5,7 72 80 90 mv rms audio output l/r imbalance 4,7,10 ?? 1 db audio frequency response low 3 ?3 db ? ? 30 hz audio frequency response high 3 ?3 db 15 ? ? khz audio mono s/n 4,3,5,7,11 ?63? db audio thd 4,7,10 ?0.1? % de-emphasis time constant fm_deemphasis = 2 70 75 80 s fm_deemphasis = 1 45 50 54 s audio output load resistance 3,11 r l single-ended 10 ? ? k ? audio output load capacitance 3,11 c l single-ended ? ? 50 pf seek/tune time 3 rclk tolerance =100ppm ? ? 60 ms/channel powerup time 3 from powerdown ? ? 110 ms rssi offset 12 input levels of 8 and 60 dbv emf ?3 ? 3 db notes: 1. additional testing information is available in ?an388: si470x/1x/2x/3x/4x evaluatio n board test procedure.? volume = maximum for all tests. tested at rf = 98.1 mhz. 2. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout, and design guidelines.? silico n laboratories will evaluate schematics and layouts for qualified customers. 3. guaranteed by characterization. 4. f mod =1khz, 75 s de-emphasis, mono = enabled, and l = r unless noted otherwise. 5. ? f = 22.5 khz. 6. b af = 300 hz to 15 khz, a-weighted. 7. v emf =1 mv. 8. analog output mode. 9. |f 2 ? f 1 | > 2 mhz, f 0 =2xf 1 ? f 2 . agc is disabled. 10. ? f = 75 khz. 11. at lout and rout pins. 12. at temperature (25 c).
si4730/31/34/35-d60 16 rev. 1.1 table 9. am/sw/lw receiver characteristics 1,2 (v a = 2.7 to 5.5 v, v a = 1.62 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit input frequency f rf long wave (lw) 153 ? 279 khz medium wave (am) 520 ? 1710 khz short wave (sw) 2.3 ? 26.1 mhz sensitivity 3,4,5 (s+n)/n = 26 db ? 25 35 v emf large signal voltage handling 5,6 thd < 8% ? 300 ? mv rms power supply rejection ratio 5 ? v dd =100 mv rms , 100 hz ? 40 ? db audio output voltage 3,7 54 60 67 mv rms audio s/n 3,4,7 ?60 ? db audio thd 3,7 ? 0.1 0.5 % antenna inductance 5,8 long wave (lw) ? 2800 ? h medium wave (am) 180 ? 450 h powerup time 5 from powerdown ? ? 110 ms notes: 1. additional testing information is available in ?an388: si470x/1x/2x/3x/4x evaluatio n board test procedure.? volume = maximum for all tests. tested at rf = 520 khz. 2. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout, and design guidelines.? silico n laboratories will evaluate schematics and layouts for qualified customers. 3. fmod = 1 khz, 30% modulation, 2 khz channel filter. 4. b af = 300 hz to 15 khz, a-weighted. 5. guaranteed by characterization. 6. see ?an388: si470x/1x/2x/3x/4x evaluation b oard test procedure? for evaluation method. 7. v in = 5 mvrms. 8. stray capacitance on antenna and board must be < 10 pf to achieve full tuning range at higher inductance levels.
si4730/31/34/35-d60 rev. 1.1 17 table 10. ac receiver characteristics?auxin analog to digital converter (v a = 2.7 to 5.5 v, v d = 1.62 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit total harmonic distortion + noise thd+n f = 1 khz; measured 20 hz?20 khz ? 0.035 0.06 % dynamic range/signal to noise ratio snr f = 1 khz at ?60 dbfs a-weighted ?85 ? db f = 1 khz at ?60 dbfs non-weighted ?78 ? db crosstalk f = 1 khz with 3% bandpass filter ?90 ? db gain mismatch ? 0.03 ? db gain drift ? 100 ? ppm/c input sample rate f s ? 48 ? khz input voltage v ai ??1.8 v pkpk input resistance r ai liatten[1:0] ? 60 ? k ? input capacitance c ai ?10 ? pf table 11. digital filter characteristics?auxin analog to digital converter (v a = 2.7 to 5.5 v, v d = 1.62 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit passband frequency response ?0.1 db 0.02 ? 20 khz passband ripple 20?20 khz ?0.1 ? 0.1 db stopband corner frequency 25 ? ? khz stopband attenuation 70 ? ? db
si4730/31/34/35-d60 18 rev. 1.1 table 12. reference clock and crystal characteristics (v a = 2.7 to 5.5 v, v d = 1.62 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit reference clock rclk supported frequencies 1 31.130 32.768 40,000 khz rclk frequency tolerance 2 ?100 ? 100 ppm refclk_prescale 1 ? 4095 refclk 31.130 32.768 34.406 khz crystal oscillator crystal oscillator frequency ? 32.768 ? khz crystal frequency tolerance 2 ?100 ? 100 ppm board capacitance ? ? 3.5 pf esr ? ? 50 ?? cl 3 71222pf cl?single ended 3 14 24 44 pf notes: 1. the si473x-d60 divides the rclk input by refclk_prescale to obtain refclk. there are some rclk frequencies between 31.130 khz and 40 mhz that are not suppor ted. for more details, see table 6 of ?an332: si47xx programming guide?. 2. a frequency tolerance of 50 ppm is required for fm seek/t une using 50 khz channel spacing and am seek/tune in sw frequencies. 3. guaranteed by characterization. table 13. thermal conditions parameter symbol min typ max unit thermal resistance* ? ja ?80?c/w ambient temperature t a ?15 25 85 c junction temperature t j ??92c *note: thermal resistance assumes a multi-layer pcb with the exposed pad soldered to a topside pcb pad.
si4730/31/34/35-d60 rev. 1.1 19 table 14. absolute maximum ratings 1,2 parameter symbol value unit analog supply voltage v a ?0.5 to 5.8 v digital and i/o supply voltage v d ?0.5 to 3.9 v input current 3 i in 10 ma input voltage 3 v in ?0.3 to (v io + 0.3) v operating temperature t op ?40 to 95 ? c storage temperature t stg ?55 to 150 ? c rf input level 4 0.4 v pk notes: 1. permanent device damage may occur if the above absolu te maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. the si473x-d60 devices are high-performanc e rf integrated circuits with certain pins having an esd rating of < 2 kv hbm. handling and assembly of these devices sh ould only be done at esd-protected workstations. 3. for input pins dfs, sclk, sen, sdio, rs t, rclk, gpo1, gpo2, gpo3, and dclk. 4. at rf input pins fmi and ami.
si4730/31/34/35-d60 20 rev. 1.1 2. typical application schematic 2.1. qfn typical application schematic notes: 1. place c1 close to va pin and c4 close to vd pin. 2. all grounds connect directly to gnd plane on pcb. 3. pins 1 and 20 are no connects, leave floating. 4. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout, and design guidelines.? silico n laboratories will evaluate schematics and layouts for qualified customers. 5. pin 2 connects to the fm antenna interface, and pin 4 connects to the am antenna interface. 6. place si473x-d60 as close as possible to antenna and keep the fmi and ami traces as short as possible. c2 l2 c1 c5 x1 2 1 l1 c3 t1 3 1 c9 c6 r3 r1 r2 c3 r3 c8 c7 r1 c9 r2 c4 16 17 18 19 20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 nc fmi rfgnd ami rstb senb sclk sdio rclk vd va gnd rout lout dout nc gpo1 gpo2/int gpo3/dclk dfs si473x rfgnd ami gpo3 rclk rin dout dout dclk dfs dfs gp03/dclk lout rout lin optional: for crystal osc 1.62 to 3.6 v fm antenna optional: digital audio out opmode: 0x5b, 0x0b optional: am air loop antenna 2.7 to 5.5 v optional: auxin/digital audio out d60 13 si473x 14 17 15 16 opmode: 0xb0, 0xb5 senb sclk sdio rclk vd va rout lout dout dfs gpo3/dclk gpo1 gpo2/int rstb
si4730/31/34/35-d60 rev. 1.1 21 2.2. ssop typical application schematic notes: 1. place c1 close to va and c4 close to vd pin. 2. all grounds connect directly to gnd plane on pcb. 3. pins 6 and 7 are no connects, leave floating. 4. pins 10 and 11 are unused. tie these pins to gnd. 5. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout, and design guidelines.? silico n laboratories will evaluate schematics and layouts for qualified customers. 6. pin 8 connects to the fm antenna interface, and pin 12 connects to the am antenna interface. 7. place si473x-d60 as close as possible to antenna and keep the fmi and ami traces as short as possible. r3 r1 c3 l1 c9 t1 3 1 l2 c2 c4 c1 c3 r2 r2 c9 r1 c7 c8 r3 x1 2 1 c5 c6 13 14 15 16 17 18 19 20 21 22 23 24 12 11 10 9 8 7 6 5 4 3 2 1 dout dfs gpo3/dclk gpo2/int gpo1 nc nc fmi rfgnd nc nc ami lout rout dbyp va vd rclk sdio sclk senb rstb gnd gnd si473x rfgnd ami gpo3 rclk rin dout dout dclk dfs dfs gp03/dclk lout rout lin opmode: 0xb0, 0xb5 optional: am air loop antenna optional: for crystal osc fm antenna optional: auxin/digital audio out si473x 2 1 vd d60 3 24 23 opmode: 0x5b, 0x0b optional: digital audio out 1.62 to 3.6 v 2.0 to 5.5 v va dout dfs gpo3/dclk lout rout rclk sdio sclk senb rstb gpo1 gpo2/int
si4730/31/34/35-d60 22 rev. 1.1 3. bill of materials 3.1. qfn/ssop bill of materials table 15. si473x-d60 qfn/ssop bill of materials component(s) value/description supplier c1 supply bypass capacitor, 22 nf, 20%, z5u/x7r murata c2 coupling capacitor, 1 nf, 20%, z5u/x7r murata c3 coupling capacitor, 0.47 f, 20%, z5u/x7r murata c4 supply bypass capacitor, 100 nf, 10%, z5u/x7r murata l1 ferrite loop stick, 180?450 hjiaxin u1 si47xx am/fm radio tuner silicon laboratories optional components c5, c6 crystal load capacitors, 22 pf, 5%, cog (optional for crystal oscillator) venkel c7 coupling capacitor, 0.39 f, 2 0 % , z 5 u / x 7 r (optional for auxin) murata c8 coupling capacitor, 0.39 f, 2 0 % , z 5 u / x 7 r (optional for auxin) murata c9 noise mitigating capacitor, 2~5 pf (optional for digital audio) murata r1 resistor, 600 ? (optional for digital audio) venkel r2 resistor, 2 k ? (optional for digital audio) venkel r3 resistor, 2 k ? (optional for digital audio) venkel l2 air loop, 10-20 h (optional for am input) jiaxin t1 transformer, 1:5 turns ratio (optional for am input) jiaxin, umec x1 32.768 khz crystal (optional for crystal oscillator) epson
si4730/31/34/35-d60 rev. 1.1 23 4. functional description 4.1. overview figure 7. functional block diagram the si473x-d60 cmos am/fm radio receiver ic integrates the complete tuner function from antenna input to audio output, including a stereo audio auxin adc input for converting analog audio to digital signals. this feature enables a cost-efficient digital audio platform for consumer electronics applications with high cell phone noise immunity, superior radio performance, and high fidelity audio powe r amplification. offering unmatched integration and pcb space savings, the si473x-d60 requires only a few external components and less than 15 mm 2 of board area, excluding the antenna inputs. the si473x-d60 am/fm radio provides the space savings and low power consumption necessary for portable devices while delivering the high performance and design simplicity desired for all am/fm solutions. leveraging silicon laborator ies' proven and patented si4700/01 fm tuner's digital low intermediate frequency (low-if) receiver architecture, the si473x-d60 delivers superior rf performance and interference rejection in the am, fm, sw, and lw bands. the high level of integration and complete system production test simplifies design-in, increa ses system quality, and improves reliability an d manufacturability. the si473x-d60 is a feature- rich solution that includes advanced seek algorithms, soft mute, auto-calibrated digital tuning, fm stereo processing and advanced audio processing. in addition, the si473x-d60 provides analog and digital audio outputs and a programmable reference clock. the device supports i 2 c-compatible 2-wire control interface, and a si4700/01 backwards-compatible 3-wire control interface. the si473x-d60 utilizes digital signal processing to achieve high fidelity, opti mal performance, and design flexibility. the chip provides excellent pilot rejection, selectivity, and unmatche d audio performance, and offers both the manufacturer and the end-user extensive programmability and a better listening experience. the si4731/35 incorporates a digital signal processor for the european radio data system (rds) and the north american radio broadcast data system (rbds) including all required symbol decoding, block synchronization, error detection, and error correction functions. using this feat ure, the si4731/35 enables broadcast data such as stat ion identification and song name to be displayed to the user. adc si473x-d60 dsp dac lout rout afc gpo/dclk ldo va 2.7~5.5 v rds (si4731/ 35) ami vd 1.62~3.6 v sen control interface sclk lna agc lna agc gnd adc mux mux dac low-if sdio rst digital audio dfs dout lin rin rclk am / lw ant rfgnd fmi fm / sw ant
si4730/31/34/35-d60 24 rev. 1.1 4.2. operating modes the si473x-d60 operates in either an fm receive, am receive, or audio auxin ad c mode. in fm mode, radio signals are received on fmi and processed by the fm front-end circuitry. in am mode, radio signals are received on ami and processed by the am front-end circuitry. in audio au xin adc mode, stereo audio signals on lin/rin are sampled, converted to digital, filtered, and decimated to 32, 44.1, or 48 khz for the i 2 s digital audio interface. in addition to the receiver mode, there is a clocking mode to choose to clock the si473x- d60 from a reference clock or crystal. on the si473x- d60, there is an audio output mode to choose between an analog and/or digital audio output. in the analog audio output mode, rout and lout are used for the audio output pins. in the digital audio mode, dout, dfs, and dclk pins are used. concurrent analog/digital audio output mode is also available requiring all five pins. 4.3. fm receiver the si473x-d60 fm receiver is based on the proven si4700/01 fm tuner. the receiver uses a digital low-if architecture allowing the elimination of external components and factory adjustments. the si473x-d60 integrates a low noise amplifier (lna) supporting the worldwide fm broadcast band (64 to 108 mhz). an agc circuit controls the gain of the lna to optimize sensitivity and rejection of strong interferers. an image- reject mixer downconverts th e rf signal to low-if. the quadrature mixer output is amplified, filtered, and digitized with high resolution analog-to-digital converters (adcs). this advanced architecture allows the si473x-d60 to perform channel selection, fm demodulation, and stereo aud io processing to achieve superior performance compared to traditional analog architectures. 4.4. am receiver the highly-integrated si473x-d60 supports worldwide am band reception from 520 to 1710 khz using a digital low-if architecture with a minimum number of external components and no manual alignment required. this digital low-if architecture allows for high-precision filtering offering excellent selectivity and snr with minimum variation across the am band. the dsp also provides adjustable channel step sizes in 1 khz increments, am demodulation, soft mute, seven different channel bandwidth filters, and additional features, such as a programmable automatic volume control (avc) maximum gain allowing users to adjust the level of background noise. similar to the fm receiver, the integrated lna and agc optimize sensitivity and rejection of strong interferers allowing better reception of weak stations. the si473x-d60 provides highly-accurate digital am tuning without factory adjustments. to offer maximum flexibility, the receiver suppo rts a wide range of ferrite loop sticks from 180?450 h. an air loop antenna is supported by using a transformer to increase the effective inductance from the air loop. using a 1:5 turn ratio inductor, the inductance is increased by 25 times and easily supports all typical am air loop antennas which generally vary between 10 and 20 h. 4.5. sw receiver the si4734/35 is the first fully integrated ic to support am and fm, as well as short wave (sw) band reception from 2.3 to 26.1 mhz fully covering the 120 meter to 11 meter bands. the si4734/35 offers extensive shortwave features such as continuous digital tuning with minimal discrete components and no factory adjustments. other sw features include adjustable channel step sizes in 1 khz increments, adjustable channel bandwidth settings, advanced seek algorithm, and soft mute. the si4734/35 uses the fm antenna to capture short wave signals. these signals are then fed directly into the ami pin in a wide band configuration. see "an332: si47xx programming guide? and ?an383: si47xx antenna and schematic guidelines" for more details. 4.6. lw receiver the si4734/35 supports the long wave (lw) band from 153 to 279 khz. the highly integrated si4734/35 offers continuous digital tuning with minimal discrete components and no factory adjustments. the si4734/35 also offers adjustable channel step sizes in 1 khz increments, adjustable channel bandwidth settings, advanced seek algorithm, and soft mute. the si4734/35 uses a separate ferrite bar antenna to capture long wave signals. 4.7. stereo audio auxin adc the si473x-d60 stereo audio auxin adc can be multiplexed between low-if input for radio operation and analog audio input for high fidelity data conversion at 32, 44.1, or 48 khz sample rate. when operated in adc-mode, the si473x-d60 supports i2s digital audio output only (no analog output) while enabling the analog inputs and the stereo adc.
si4730/31/34/35-d60 rev. 1.1 25 4.8. digital audio interface the digital audio interface operates in slave mode and supports a variety of msb-first audio data formats including i2s and left-justified modes. the interface has three pins: digital data input (din), digital frame synchronization input (dfs), and a digital bit synchronization input clock (dclk). the si473x-d60 supports a number of industry-standard sampling rates including 32, 44.1, and 48 khz. the digital audio interface enables low-power operation by eliminating the need for redundant dacs and adcs on the audio baseband processor. 4.8.1. audio data formats the digital audio interface operates in slave mode and supports three different audio data formats: ? i2s ? left-justified ? dsp mode in i2s mode, by default the msb is captured on the second rising edge of dclk following each dfs transition. the remaining bits of the word are sent in order, down to the lsb. the left channel is transferred first when the dfs is low, and the right channel is transferred when the dfs is high. in left-justified mode, by de fault the msb is captured on the first rising edge of dclk following each dfs transition. the remaining bits of the word are sent in order, down to the lsb. the left channel is transferred first when the dfs is high, and the right channel is transferred when the dfs is low. in dsp mode, the dfs becomes a pulse with a width of 1dclk period. the left channel is transferred first, followed right away by the right channel. there are two options in transferring the digital audio data in dsp mode: the msb of the left channel can be transferred on the first rising edge of dcl k following the dfs pulse or on the second rising edge. in all audio formats, depend ing on the word size, dclk frequency, and sample rates, there may be unused dclk cycles after the lsb of each word before the next dfs transition and msb of the next word. in addition, if preferred, the user can configure the msb to be captured on the falling ed ge of dclk via properties. the number of audio bits can be configured for 8, 16, 20, or 24 bits. 4.8.2. audio sample rates the device supports a number of industry-standard sampling rates including 32 , 44.1, and 48 khz. the digital audio interface enables low-power operation by eliminating the need for re dundant dacs on the audio baseband processor.
si4730/31/34/35-d60 26 rev. 1.1 figure 8. i2s digital audio format figure 9. left-justified digital audio format figure 10. dsp digital audio format left channel right channel 1 dclk 1 dclk 13 2n n-1 n-2 13 2n n-1 n-2 lsb msb lsb msb dclk dout dfs inverted dclk (ofall = 1) (ofall = 0) i 2 s (omode = 0000) left channel right channel 13 2n n-1 n-2 13 2 n n-1 n-2 lsb msb lsb msb dclk dout dfs inverted dclk (ofall = 1) (ofall = 0) left-justified (omode = 0110) 13 2n n-1 n-2 n n-1 n-2 lsb msb lsb msb dclk dout (msb at 1 st rising edge) dfs 13 2 left channel right channel 1 dclk (ofall = 0) (omode = 1100) 13 2n n-1 n-2 n n-1 n-2 lsb msb lsb msb 13 2 left channel right channel dout (msb at 2 nd rising edge) (omode = 1000)
si4730/31/34/35-d60 rev. 1.1 27 4.9. stereo audio processing the output of the fm demodulator is a stereo multiplexed (mpx) signal. the mpx standard was developed in 1961, and is used worldwide. today's mpx signal format consists of left + right (l+r) audio, left ? right (l?r) audio, a 19 khz pilot tone, and rds/rbds data as shown in figure 11 below. figure 11. mpx signal spectrum 4.9.1. stereo decoder the si473x-d60's integrated stereo decoder automatically decodes the mpx signal using dsp techniques. the 0 to 15 khz (l+r) signal is the mono output of the fm tuner. stereo is generated from the (l+r), (l?r), and a 19 khz pilot tone. the pilot tone is used as a reference to recover the (l?r) signal. output left and right channels are obtained by adding and subtracting the (l+r) and (l?r) signals respectively. 4.9.2. stereo-mono blending adaptive noise suppression is employed to gradually combine the stereo left and right audio channels to a mono (l+r) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. three metrics, received signal strength indicator (rssi), si gnal-to-noise ratio (snr), and multipath interference, are monitored simultaneously in forcing a blend from stereo to mono. the metric which reflects the minimum signal quality takes precedence and the signal is blended appropriately. all three metrics have programmable stereo/mono thresholds and attack/relea se rates. if a metric falls below its mono threshold, the signal is blended from stereo to full mono. if all metrics are above their respective stereo thresholds, then no action is taken to blend the signal. if a metric falls between its mono and stereo thresholds, then the signal is blended to the level proportional to the metric?s value between its mono and stereo thresholds, with an associated attack and release rate. 4.10. received signal qualifiers the quality of a tuned signal can vary depending on many factors including environmental conditions, time of day, and position of the an tenna. to adequately manage the audio output and avoid unpleasant audible effects to the end-user, the si473x-d60 monitors and provides indicators of the signal quality, allowing the host processor to perform additional processing if required by the customer. the si473x-d60 monitors signal quality metrics including rssi, snr, and multipath interference on fm signals. these metrics are used to optimize signal processing and are also reported to the host processor. the signal processing algorithms can use either silicon labs' optimized settings (recommended) or be customized to modify performance. 4.11. volume control the audio output may be muted. volume is adjusted digitally by the rx_volume property. 4.12. stereo dac high-fidelity stereo digital-to-analog converters (dacs) drive analog audio signals onto the lout and rout pins. the audio output may be muted. 4.13. soft mute the soft mute feature is available to attenuate the audio outputs and minimize audible noise in very weak signal conditions. the soft mute feature is triggered by the snr metric. the snr threshold for activating soft mute is programmable, as are soft mute attenuation levels and attack and release rates. 4.14. fm hi-cut control hi-cut control is employed on audio outputs with degradation of the signal due to low snr and/or multipath interference. two metrics, snr and multipath interference, are monitored concurrently in forcing hi-cut of the audio outputs. programmable minimum and maximum thresholds are available for both metrics. the transition frequency for hi-cut is also programmable with up to seven hi-cut filter se ttings. a single set of attack and release rates for hi-cut are programmable for both metrics from a range of 2 ms to 64 s. the level of hi-cut applied can be monitored with the fm_rsq_status command. hi-cut can be disabled by setting the hi-cut filter to audio bandwidth of 15 khz. 057 53 38 23 19 15 frequency (khz) modulation level stereo audio left - right rds/ rbds mono audio left + right stereo pilot
si4730/31/34/35-d60 28 rev. 1.1 4.15. de-emphasis pre-emphasis and de-emphasis is a technique used by fm broadcasters to improve the signal-to-noise ratio of fm receivers by reducing the effects of high-frequency interference and noise. when the fm signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. the si473x-d60 incorporates a de-emphasis f ilter which attenuates high frequencies to restore a flat frequency response. two time constants are used in various regions. the de- emphasis time constant is programmable to 50 or 75 s and is set by the fm_deemphasis property. 4.16. rds/rbds processor (si4731/35 only) the si4731/35 implements an rds/rbds* processor for symbol decoding, block synchronization, error detection, and error correction. the si4731/35 device is user configurable and provides an optional interrupt when rds is synchronized, loses synchronization, and/or the user configurable rds fifo threshold has been met. the si4731/35 reports rds decoder synchronization status and detailed bit errors in the information word for each rds block with the fm_rds_status command. the range of reportable block errors is 0, 1?2, 3?5, or 6+. more than six errors indicates that the corresponding block information word contains six or more non-correctable errors or that the block checkword contains errors. the pilot does not have to be present to decode rds/rbds. *note: rds/rbds is referred to only as rds throughout the remainder of this document. 4.17. tuning the tuning frequency is directly programmed using the fm_tune_freq and am_tune_freq commands. the si473x-d60 supports channel spacing steps of 10 khz in fm mode and 1 khz in am mode. 4.18. seek the si473x-d60 seek functionality is performed completely on-chip and w ill search up or down the selected frequency band for a valid channel. a valid channel is qualified according to a series of programmable signal indicators and thresholds. the seek function can be made to stop at the band edge and provide an interrupt, or wrap the band and continue seeking until arriving at the original departure frequency. the device sets interrupts with found valid stations or, if the seek results in zero fo und valid stations, the device indicates failure and again sets an interrupt. refer to ?an332: si47xx programming guide?. the si473x-d60 uses rssi, snr, and afc to qualify stations. most of these variables have programmable thresholds for modifying the seek function according to customer needs. rssi is employed first to screen all possible candidate stations. snr and afc are subsequently used in screening the rssi qua lified stations. the more thresholds the system engages, the higher the confidence that an y found stations will indeed be valid broadcast stations. the si473x-d60 defaults set rssi to a mid-level threshold and add an snr threshold set to a level delivering acceptable audio performance. this trade-off will eliminate very low rssi stations while keeping the seek time to ac ceptable levels. generally, the time to auto-scan and store valid channels for an entire fm band with all thresholds engaged is very short depending on the band conten t. seek is initiated using the fm_seek_start command . the rssi, snr, and afc threshold settings are adjustable using properties. 4.19. reference clock the si473x-d60 reference clock is programmable, supporting rclk frequencies listed in table 12, ?reference clock and crystal characteristics,? on page 18. refer to table 2, ?dc characteristics,? on page 6 for switching voltage levels and table 12 for frequency tolerance information. an onboard crystal oscillator is available to generate the 32.768 khz reference when an external crystal and load capacitors are provided. refe r to "2. typical application schematic" on page 20. this mode is enabled using the power_up command. refer to ?an332: si47xx programming guide?. the si473x-d60 performance may be affected by data activity on the sdio bus when using the integrated internal oscillator. sdio activity results from polling the tuner for status or commun icating with other devices that share the sdio bus. if there is sdio bus activity while the si473x-d60 is performing the seek/tune function, the crystal oscilla tor may experience jitter, which may result in mistunes , false stops, and/or lower snr. for best seek/tun e results, silicon laboratories recommends that all sdio data traffic be suspended during si473x-d60 seek and tune operations. this is achieved by keeping the bus quiet for all other devices on the bus, and delaying tu ner polling until the tune or seek operation is complete. the seek/tune complete (stc) interrupt should be us ed instead of polling to determine when a seek/tune operation is complete.
si4730/31/34/35-d60 rev. 1.1 29 4.20. control interface a serial port slave interface is provided, which allows an external controller to send commands to the si473x- d60 and receive responses from the device. the serial port can operate in two bus modes: 2-wire mode and 3- wire mode. the si473x-d60 selects the bus mode by sampling the state of the gpo1 and gpo2 pins on the rising edge of rst . the gpo1 pin includes an internal pull-up resistor, which is connected while rst is low, and the gpo2 pin includes an internal pull-down resistor, which is connected while rst is low. therefore, it is only necessary for the user to actively drive pins which differ from these states. see table 16. after the rising edge of rst , the pins gpo1 and gpo2 are used as general purpose output (o) pins, as described in section ?4.21. gpo outputs?. in any bus mode, commands may only be sent after v d and v a supplies are applied. in any bus mode, before sending a command or reading a response, the user must first read the status byte to ensure that the device is ready (cts bit is high). 4.20.1. 2-wire cont rol interface mode when selecting 2-wire mode, the user must ensure that sclk is high during the rising edge of rst , and stays high until after the first start condition. also, a start condition must not occur within 300 ns before the rising edge of rst . the 2-wire bus mode uses only the sclk and sdio pins for signaling. a transaction begins with the start condition, which occurs when sdio falls while sclk is high. next, the user drives an 8-bit control word serially on sdio, which is captur ed by the device on rising edges of sclk. the control word consists of a 7-bit device address, followed by a read/write bit (read = 1, write = 0). the si473x-d60 acknowledges the control word by driving sdio low on the next falling edge of sclk. although the si473x-d60 will respond to only a single device address, this address can be changed with the sen pin (note that the sen pin is not used for signaling in 2-wire mode). refer to ?an332: si47xx programming guide? for write operations, the user then sends an 8-bit data byte on sdio, which is captured by the device on rising edges of sclk. the si473x-d60 acknowledges each data byte by driving sdio low for one cycle, on the next falling edge of sclk. the us er may write up to 8 data bytes in a single 2-wire transaction. the first byte is a command, and the next seven bytes are arguments. for read operations, after the si473x-d60 has acknowledged the control byte , it will drive an 8-bit data byte on sdio, changing the state of sdio on the falling edge of sclk. the user acknowledges each data byte by driving sdio low for on e cycle, on the next falling edge of sclk. if a data byte is not acknowledged, the transaction will end. the user may read up to 16 data bytes in a single 2-wire transaction. these bytes contain the response data from the si473x-d60. a 2-wire transaction ends with the stop condition, which occurs when sdio rises while sclk is high. for details on timing specific ations and diagrams, refer to table 4, ?2-wire control interface characteristics? on page 9; figure 2, ?2-wire control interface read and write timing parameters,? on page 10, and figure 3, ?2- wire control interface read and write timing diagram,? on page 10. 4.20.2. 3-wire cont rol interface mode when selecting 3-wire mode, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . the 3-wire bus mode uses the sclk, sdio, and sen _ pins. a transaction begins when the user drives sen low. next, the user drives a 9-bit control word on sdio, which is captured by the device on rising edges of sclk. the control word consists of a 9-bit device address (a7:a5 = 101b), a read/write bit (read = 1, write = 0), and a 5-bit register address (a4:a0). for write operations, the control word is followed by a 16-bit data word, which is captured by the device on rising edges of sclk. for read operations, the cont rol word is followed by a delay of one-half sclk cycle for bus turn-around. next, the si473x-d60 will drive the 16-bit read data word serially on sdio, changing the state of sdio on each rising edge of sclk. a transaction ends when the user sets sen high, then pulses sclk high and low one final time. sclk may either stop or continue to toggle while sen is high. in 3-wire mode, commands are sent by first writing each argument to register(s) 0xa1?0xa3, then writing the command word to register 0xa0. a response is retrieved by reading registers 0xa8?0xaf. for details on timing specific ations and diagrams, refer to table 5, ?3-wire control in terface characteristics,? on page 11; figure 4, ?3-wire control interface write table 16. bus mode select on rising edge of rst bus mode gpo1 gpo2 2-wire 1 0 3-wire 0 (must drive) 0
si4730/31/34/35-d60 30 rev. 1.1 timing parameters,? on page 11, and figure 5, ?3-wire control interface read timing parameters,? on page 11. 4.21. gpo outputs the si473x-d60 provides three general-purpose output pins. the gpo pins can be configured to output a constant low, constant high, or high-impedance. the gpo pins can be reconfigured as specialized functions. 4.22. firmware upgrades the si473x-d60 contains on-chip program ram to accommodate minor changes to the firmware. this allows silicon labs to pr ovide future firmware updates to optimize the characteristic s of new radio designs and those already deployed in the field. 4.23. reset, powerup, and powerdown setting the rst pin low will disable analog and digital circuitry, reset the registers to their default settings, and disable the bus. setting the rst pin high will bring the device out of reset. a powerdown mode is available to reduce power consumption when the part is idle. putting the device in powerdown mode will disable analog and digital circuitry while keeping the bus active. 4.24. 2 v operation (ssop only) the si473x-d60 is capable of operating down to 2 v as the battery drains in an application. any power-up or reset is not guaranteed to work below the dc characteristics defined in table 2. this capability enables a much longer run time in battery operated devices. 4.25. programmi ng with commands to ease development time and offer maximum customization, the si473x-d 60 provides a simple yet powerful software interface to program the receiver. the device is programmed using commands, arguments, properties, and responses. to perform an action, the user writes a command byte and associated arguments, causing the chip to execute the given command. commands control an action such as powerup the device, shut down the device, or tune to a station. arguments are specific to a given command and are used to modify the command. properties are a special command argument used to modify the default chip operation and are generally configured immediately after powerup. examples of properties are de-emphasis level, rssi seek threshold, and soft mute attenuation threshold. responses provide the user information and are echoed after a command and associated arguments are issued. all commands provi de a 1-byte status update, indicating interrupt and clear-to-send status information. for a detailed description of the commands and properties for the si473x-d60, see ?an332: si47xx programming guide.?
si4730/31/34/35-d60 rev. 1.1 31 5. pin descriptions 5.1. si473x-d60-gm pin number(s) name description 1, 20 nc no connect. leave floating. 2 fmi fm rf inputs. fmi should be connected to the antenna trace. 3 rfgnd rf ground. connect to ground plane on pcb. 4 ami am rf input. ami should be connected to the am antenna. 5 rst device reset input (active low). 6 sen serial enable input (active low). 7 sclk serial clock input. 8 sdio serial data input/output. 9 rclk external refere nce oscillator input. 10 v d digital and i/o supply voltage. 11 v a analog supply voltage. may be connected directly to battery. 12, gnd pad gnd ground. connect to ground plane on pcb. 13 rout/[dout] right audio line output for analog output mode. 14 lout/[dfs] left audio line output for analog output mode. 15 dout/[lin] digital output data for digital output mode or left channel input for auxin adc mode. 16 dfs/[rin] digital frame synchronization input for digital output mode or right channel input for auxin adc mode. 17 gpo3/[dclk] general purpose output, crystal osc illator, or digital bit synchronous clock input in digital output mode. 18 gpo2/[int] general purpose output or interrupt pin. 19 gpo1 general purpose output. gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 gpo2/[int] vd dout/[lin] lout/[dfs] rout/[dout] gnd rst nc ami rclk sdio va fmi rfgnd gpo3/[dclk] nc gpo1 dfs/[rin] sclk sen
si4730/31/34/35-d60 32 rev. 1.1 5.2. si473x-d60-gu pin number(s) name description 1 dout/[lin] digital output data for digital out put mode or left channel input for aux in adc mode. 2 dfs/[rin] digital frame synchronization input for digital output mode or right channel input for auxin adc mode. 3 gpo3/[dclk] general purpose output, crystal osc illator, or digital bit synchronous clock input in digital output mode. 4 gpo2/[int] general purpose output or interrupt pin. 5 gpo1 general purpose output. 6,7 nc no connect. leave floating. 8 fmi fm rf inputs. fmi should be connected to the antenna trace. 9 rfgnd rf ground. connect to ground plane on pcb. 10,11 nc unused. tie these pins to gnd. 12 ami am/sw/lw rf input. 13,14 gnd ground. connect to ground plane on pcb. 15 rst device reset input (active low). 16 sen serial enable input (active low). 17 sclk serial clock input. 18 sdio serial data input/output. 19 rclk external refere nce oscillator input. 20 v d digital and i/o supply voltage. 21 v a analog supply voltage. may be connected directly to battery. 22 dbyp bypass capacitor. 23 rout/[dout] right audio line output in analog output mode. 24 lout/[dfs] left audio line output in analog output mode. lout/[dfs] rout/[dout] dbyp vd gpo2/[int] gpo3/[dclk] dout/[lin] dfs/[rin] 1 2 3 4 5 6 7 8 9 10 11 12 gpo1 va sdio nc nc rclk sen fmi rfgnd sclk gnd nc nc rst gnd ami 24 23 22 21 20 19 18 17 16 15 14 13
si4730/31/34/35-d60 rev. 1.1 33 6. ordering guide part number 1 description package type operating temperature/voltage SI4730-D60-GM am/fm broadcast radio receiver qfn pb-free ?20 to 85 c 2.7 to 5.5 v si4730-d60-gu 2 ssop pb-free si4731-d60-gm am/fm broadcast radio receiver with rds/rbds qfn pb-free ?20 to 85 c 2.7 to 5.5 v si4731-d60-gu 2 ssop pb-free si4734-d60-gm am/fm/sw/lw broadcast radio receiver qfn pb-free ?20 to 85 c 2.7 to 5.5 v si4734-d60-gu 2 ssop pb-free si4735-d60-gm am/fm/sw/lw broadcast radio receiver with rds/rbds qfn pb-free ?20 to 85 c 2.7 to 5.5 v si4735-d60-gu 2 ssop pb-free notes: 1. add an ?(r)? at the end of the device part number to denote tape and reel option. 2. ssop devices operate down to v a = 2 v at 25 c.
si4730/31/34/35-d60 34 rev. 1.1 7. package outline 7.1. si473x-d60 qfn figure 12 illustrates the package details for the si473x. table 17 lists the val ues for the dimensions shown in the illustration. figure 12. 20-pin quad flat no-lead (qfn) table 17. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.50 0.55 0.60 f 2.53 bsc a1 0.00 0.02 0.05 l 0.35 0.40 0.45 b 0.200.250.30 l1 0.00 ? 0.10 c 0.27 0.32 0.37 aaa ? ? 0.05 d 3.00 bsc bbb ? ? 0.05 d2 1.65 1.70 1.75 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 3.00 bsc eee ? ? 0.10 e2 1.65 1.70 1.75 notes: 1. all dimensions are shown in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si4730/31/34/35-d60 rev. 1.1 35 7.2. si473x-d60 ssop figure 13 illustrates the package details for the si473x. table 18 lists the val ues for the dimensions shown in the illustration. figure 13. 24-pin ssop table 18. package dimensions dimension min nom max a??1.75 a1 0.10 ? 0.25 b0.20?0.30 c0.10?0.25 d 8.65 bsc e 6.00 bsc e1 3.90 bsc e 0.635 bsc l0.40?1.27 l2 0.25 bsc 0 ? 8 aaa 0.20 bbb 0.18 ccc 0.10 ddd 0.10 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec so lid state outline mo-137, variation ae. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si4730/31/34/35-d60 36 rev. 1.1 8. pcb land pattern 8.1. si473x-d60 qfn figure 14 illustrates the pcb land patt ern details for the si473x -d60-gm qfn. table 19 lists the values for the dimensions shown in the illustration. figure 14. pcb land pattern
si4730/31/34/35-d60 rev. 1.1 37 table 19. pcb land pattern dimensions symbol millimeters symbol millimeters min max min max d 2.71 ref ge 2.10 ? d2 1.60 1.80 w ? 0.34 e 0.50 bsc x ? 0.28 e 2.71 ref y 0.61 ref e2 1.60 1.80 ze ? 3.31 f 2.53 bsc zd ? 3.31 gd 2.10 ? notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m- 1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum mate rial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes: solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes: stencil design 1. a stainless steel, laser-cut, and electro-polis hed stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 1.45 x 1.45 mm square aperture should be used for the center pad. this provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. notes: card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is pe r the jedec/ipc j-std-020 specification for small body components.
si4730/31/34/35-d60 38 rev. 1.1 8.2. si473x-d60 ssop figure 15 illustrates the pcb land patte rn details for the si473x -d60-gu ssop. table 20 lists the values for the dimensions shown in the illustration. figure 15. pcb land pattern table 20. pcb land pattern dimensions dimension min max c5.205.30 e 0.635 bsc x0.300.40 y1 1.50 1.60 general: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design: 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design: 4. a stainless steel, laser-cut and electro- polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. card assembly: 7. a no-clean, type-3 solder paste is recommended. 8. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ?
si4730/31/34/35-d60 rev. 1.1 39 9. top markings 9.1. si473x-d60 top marking (qfn) 9.2. top marking explanation (qfn) mark method: yag laser line 1 marking: part number 30 = si4730, 31 = si4731, 34 = si4734, 35 = si4735. firmware revision 60 = firmware revision 6.0. line 2 marking: die revision d = revision d die. ttt = internal code internal tracking code. line 3 marking: circle = 0.5 mm diameter (bottom-left justified) pin 1 identifier. y = year ww = workweek assigned by the assembly hous e. corresponds to the last significant digit of the year and work week of the mold date. 3060 dttt yww 3160 dttt yww 3460 dttt yww 3560 dttt yww
si4730/31/34/35-d60 40 rev. 1.1 9.3. si473x-d60 top marking (ssop) 9.4. top marking explanation (ssop) mark method: yag laser line 1 marking: part number 4730 = si4730; 4731 = si4731; 4734 = si4734; 4735 = si4735. die revision d = revision d die. firmware revision 60 = firmware revision 6.0. package type gu = 24-pin ssop pb-free package line 2 marking: yy = year ww = work week tttttt = manufacturing code assigned by the assembly house. 473xd60gu yywwtttttt
si4730/31/34/35-d60 rev. 1.1 41 10. additional reference resources contact your local sales representative s for more information or to obtain copies of the following references: ? en55020 compliance test certificate ? an332: si47xx programming guide ? an383: si47xx antenna, schematic, layout, and design guidelines ? an388: si470x/1x/2x/3x/4x eval uation board test procedure ? si47xx evb user?s guide ? customer support site: www.silabs.com this site contains all application notes, evaluation b oard schematics and layouts, and evaluation software. nda is required for complete access. please visi t the silicon labs technical support web page: https://www.silabs.com/support/pa ges/contacttechnicalsupport.aspx and register to submit a technical support request.
si4730/31/34/35-d60 42 rev. 1.1 d ocument c hange l ist revision 1.0 to revision 1.1 ? updated part number throughout. ? updated pin assignments on front page. ? updated block diagram on front page. ? updated table 6, ?digital audio interface characteristics,? on page 12. ? updated table 12, ?reference clock and crystal characteristics,? on page 18. ? added table 13, ?thermal conditions,? on page 18. ? updated section "2. typica l application schematic" on page 20. ? updated section "4. functional description" on page 23. ? updated section "5. pin descriptions" on page 31.
si4730/31/34/35-d60 rev. 1.1 43 n otes :
si4730/31/34/35-d60 44 rev. 1.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: fminfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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